As the massive volumes of electronically stored and transmitted data (e.g., “big data”) continue to increase, so does the need for electronic data storage that is reliable and cost effective, yet quickly accessible (e.g., low latency). Specifically, more computing applications are requiring that increasingly larger data sets be stored in “hot” locations for high speed access. Certain non-volatile memory (NVM) storage technologies, such as magnetic hard disk drives (HDDs), can provide a reliable, low cost storage solution, yet with relatively high access latencies. Such storage technologies might be used for large volumes of data in “cold” locations that are not often accessed (e.g., data warehouses, archives, etc.). Other volatile or “dynamic” memory storage technologies, such as dynamic random access memory (DRAM), provide lower access latencies, and might be used in “hot” locations near a computing host (e.g., CPU) to offer fast access to certain data for processing. Yet, such storage technologies can have a relatively high cost and risk of data loss (e.g., on power loss). Solid state NVM, such as Flash memory, can offer an improved form factor and access latency as compared to an HDD, yet still not approach the access latency of DRAM.
In some cases, DRAM and Flash can be combined in a hybrid memory module to deliver the fast data access of the DRAM and the non-volatile data integrity (e.g., data retention) enabled by the Flash memory. One such implementation is the non-volatile dual in-line memory module (NVDIMM), which stores data in DRAM for normal operation, and stores data in Flash for backup and/or restore operations (e.g., responsive to a power loss, system crash, normal system shutdown, etc.). Specifically, for example, the JEDEC standards organization has defined the NVDIMM-N product for such backup and/or restore applications. Many NVDIMM implementations can further be registered DIMMs (RDIMMs), which can use hardware registers and other logic, such as included in a registering clock driver (RDC), to buffer the address and control signals to the DRAM devices in order to expand the capacity of the memory channels. Other NVDIMM implementations can be load-reduced DIMMs (LRDIMMs), which can include data buffers to buffer the data signals in order to reduce the loading on the data bus and expand the capacity of the memory channels.
Unfortunately, legacy NVDIMM architectures can have functional and performance limitations. Specifically, some NVDIMMs can exhibit throughput limitations associated with the non-volatile memory controller (NVC) communications interface used for DRAM read and write commands during data backup and data restore operations. For example, some NVC communications interface protocols can require 128 DRAM clock cycles per DRAM command (e.g., read, write, etc.) issued from the non-volatile memory controller. Such latencies can affect the throughput of backup and/or restore operations, resulting in high power consumption (e.g., more clock cycles). In some cases, the RDC interface to the NVC (e.g., LCOM interface) and/or the DRAM devices can also limit the options for connecting the DRAM devices to the NVC, resulting in an increased chip layout area and a corresponding increase per chip cost.
Also, some NVDIMMs might restrict non-volatile memory controller (NVC) resource access when in a host control mode. For example, such restrictions might be implemented so as to avoid impacting access to certain resources (e.g., control setting registers) by the host memory controller when in a host control mode. In some cases, the NVC resource access (e.g., read access) can be limited in both the host control mode and an NVC control mode. The foregoing NVC resource access restrictions might cause the NVC to remain idle when it might otherwise be used to reduce the load on the host and/or prepare certain settings in advance of an event (e.g., data backup, data restore, etc.), resulting in decreased power efficiency and/or decreased throughput of the memory system.
In some cases, some NVDIMMs can also exhibit certain functional restrictions, long latencies, and high power consumption when programming certain DRAM device settings in a non-volatile memory controller (NVC) control mode, such as that invoked during data backup and data restore operations. For example, the NVC control mode might require different mode register settings for the DRAM devices as compared to the mode register settings established for the host control mode. In certain NVDIMM implementations, the NVC might have access to only certain bits of the mode register settings established in the host control mode such that any mode register set (MRS) commands issued from the NVC might overwrite certain settings that were desired to remain unchanged. Further, the MRS commands issued from the NVC can comprise extended clock cycles as compared to those issued directly to the DRAM devices, resulting in increased latencies and increased power consumption attributed to the programming of the mode register settings when switching into and out of the NVC control mode.
Techniques are needed to address the problems of:                implementing a hybrid memory module that overcomes the throughput limitations of the NVC communications interface used for DRAM read and write commands during data backup and data restore operations;        implementing a hybrid memory module that expands the NVC resource access, yet does not impact host memory controller resource access, when in a host control mode; and        implementing a hybrid memory module that exhibits enhanced programmability of the DRAM mode register settings in an NVC control mode, such as that invoked during data backup and data restore operations.        
None of the aforementioned legacy approaches achieve the capabilities of the herein-disclosed techniques, therefore, there is a need for improvements.